1. Field of the Invention
The present invention relates generally to methods and apparatus for providing a matrix of uniquely addressable locations and, more particularly, to devices that may store data in a matrix of uniquely addressable locations that may be addressed using a reduced number of address bits.
2. Related Art
Several types of devices require unique locations to be addressed. Examples of these include, but are not limited to, devices that present data such as video displays, devices that may receive and record matrix data such as imaging arrays, and devices that may interconnect internally such as logic arrays. Another type of device, a conventional disk drive, also requires unique locations to be addressed. Conventional disk drives require mechanical manipulation of the disk to access data in a particular location.
Still another type of device which requires unique locations to be addressed is a device which may store and receive data such as a computer memory. Various portions of the following discussion will deal with memory devices such as computer memories. However, the teachings herein are not limited in this respect and may be applied to any type of device that requires unique addressing.
In the context of computer memories, since the advent of the first computer, it has been realized that memory devices for storing information are an essential element of a working computer. Many types of memories for computers have been developed, such as read-only memories (ROMs) and random-access memories (RAMs) as well as magnetic and optical data storage disks. These memories are accessed for read/write operations by the central processing unit (CPU) of the computer.
As computers have gotten smaller and faster, computer and memory unit designers have recognized that their memory devices likewise need to be smaller and operate faster. This has led to very competitive research and development of smaller, faster memory units.
The basic structure upon which present computer memories are based is the row/column array configuration. This structure has been very useful, not only in the field of computer memories but also as a model for conceptually dealing with data structures in the computer science art.
FIG. 1 is an example of a prior art memory array 1. The memory array 1 includes several row address lines 2 and column address lines 3. A memory cell is typically located at the intersection of a row address line and a column address line. The memory cells are used to store information, typically digital information. Examples of memory cells are a capacitor, a transistor device, a flip-flop, or an optical data storage device. As is well known, some memory cells store only a single bit while other types may be capable of storing a block of data such as typically referred to as a xe2x80x9cwordxe2x80x9d or xe2x80x9cbytexe2x80x9d.
In order to access a particular memory cell in the memory array 1, the CPU (not shown) must access both the row and the column corresponding to the location of the memory cell in the array. This entails sending a memory location address from the CPU to the memory array 1. The address is then decoded by conventional means such as a multiplexer, and the correct memory cell of interest is then accessed. Thus, the location of each memory cell may be represented as nr,c where the r and c represent the row and column, respectively (with the first row and column being denoted as xe2x80x9c0xe2x80x9d as is conventional).
For example, in the 8xc3x978 memory array 1, if the CPU desired access to the memory cell at the intersection of the third row and the eighth column (n2,7) the CPU would have to send a binary row address of 010 to the row decoder 4 and a binary column address of 111 to the column decoder 5. The row decoder 4 and column decoder 5 are typically implemented as multiplexers. The row decoder 4 converts the three bit row input to a binary representation of 00000100. This output is then transferred to the memory array 1 through hard wired connections between the output of the row decoder 4 and the memory array 1. Thus, in order to access each row of the 8xc3x978 memory array 1, eight physical line connections (as well as the requisite multiplexer) must be included with the memory array 1. Similarly, the column decoder 5 receives the address 111 and converts it to 10000000 leading to an additional 8 lines (and a second multiplexer) to be connected to the memory array 1. Thus, a total of 16 physical line connections and two decoders are required in order to access each and every cell of the 8xc3x978 memory array 1. The interconnections and decoders require space on an integrated chip and therefore serve as a bottleneck when trying to reduce the physical size occupied by the memory array 1 and its supporting hardware.
When a memory array is configured in the manner described above, the number of address bits required to access the particular memory is determined by the size of the memory array. For example, addressing for a 64 cell, 8xc3x978 memory array 1 requires at least 6 bits, 3 for the row and 3 for the column. Thus, an inherent relationship exists in essentially all conventional memory devices between the requisite number of address bits and the number of memory cells in the memory array 1 as shown in equation (1):
addresses=2nxe2x80x83xe2x80x83(1)
where n is the number of address bits. However, this equation is deceiving; it represents the number of bits the CPU must xe2x80x9csend outxe2x80x9d in order to access a particular memory cell of the memory array 1. In actuality, the number of address bits received by the memory array 1 is equal to the number of physical line connections to the memory array 1 as discussed above. Thus, for the 8xc3x978 array discussed above, the memory array 1 actually receives 16 address bits. This is more than double the number of address bits needed to represent each of the memory cells of the array. The transmission of these extra bits requires additional wiring and thus, increases the size and complexity of memory arrays.
Thus, for a square array containing 2n memory cells, 2xc3x972n/2 lines (i.e., 2n/2 columns and 2n/2 rows) must be supplied to and embedded within the array. For example, for an array of 4096 bits (i.e., 212), 128 (i.e., 2xc3x9726) lines are necessary, even though the lower limit of binary addresses required from the CPU is only 12xe2x80x94a full order of magnitude less than the row column scheme requires. This disparity grows exponentially as the array grows in size.
Other issues related to the amount of wiring required in conventional memory devices include the complex topology necessitated by the perpendicular passage of row and column lines past one another to reach their respective connections to the cell.
In addition to the size constraints imposed by the extra wiring of a memory array, implementing a memory unit as a two-dimensional array also has other size constraints. For instance, the physical layout of the memory unit imposes a size limitation. As the amount of memory needed has increased, many novel approaches for how to layout the memory device have been developed. For example, stacking the memory units on top of one another has been proposed. This allows for an increase in memory by increasing the volume of the memory unit without increasing the amount of surface area on a computer""s mother board taken up by the memory. However, as the physical dimensions of computers have decreased, so has the available volume. Traditionally, each memory array in the stacked memory device must be individually addressed, which requires more hard wiring and address bits. Conceptually, each memory cell has a location of Xr,c,l were r, c, and l are the row, column and layer, respectively of the stacked type of memory device. A novel approach to reducing the size of such a memory is disclosed in U.S. Pat. No. 5,623,160 where interconnections between the layers of integrated circuits are conducted by vertical pillars extending from a bottom layer to a top layer. Also, several devices have attempted to reduce the size of the memory device by various types of interconnection techniques to reduce the amount of space required to provide power and ground connections to each layer of the stacked memory device.
The memory devices of the prior art were typically rigid integrated chips. At times, when repairing or modifying the internal configuration of the computer, an integrated chip could be cracked or broken. Further, having the memory device placed on an integrated chip severely limited the shape the memory device could take. For example, a memory array configured in the row/column manner somewhat predisposes the chips to take on a square shape (See e.g., FIG. 1). While the rows and columns may intersect one another at angles other than right angles, the space constraints of the memory cell which actually holds the data must fit and be connectable to the rows and columns, and this limits the row/column configuration.
In addition, there is a lower size limit dictated by the total perimeter necessary to accommodate all interconnections from all lines of the memory array to external devices. For example, with the 4096 bit array described above, the total perimeter is equal to roughly 128xc3x97P, where P is the so called xe2x80x9cpitch distancexe2x80x9d required between bonding pads. Thus one side of the square array is approximately (128xc3x97P/4) in length and the area of the array can be no less than (128xc3x97P/4)2. Since bonding pads must be large enough to accommodate ordinary wires, P is a number which cannot be reduced into the microscopic range. Therefore, even if the memory array itself is reduced to a miniscule area, the overall package cannot be reduced beyond the size dictated by the lower limits of perimeter length. In actuality, the perimeter is even greater than described above since additional grounding lines must be regularly interspersed amongst the signal lines to control inter-line capacitive interference.
The typical row/column configuration may also have inherent signal propagation delays because a signal must traverse the long narrow conduction pathways established in the memory array before it is read out.
Another source of delay may come in the form of a stabilization timing delay which is inherent in a conventional row/column accessing scheme. Typically, to access a particular memory cell, the column is addressed, allowed to stabilize, and then the row is addressed and allowed to stabilize. The timing of the stabilization has received a great deal of attention as it is related to clock cycles with various conventional schemes.
Aspects and embodiments of the present invention may overcome some or all of the above and other drawbacks to conventional addressing arrangements. Some embodiments of the present invention are directed to memory units/data storage devices. In these embodiments, aspects of the present invention include both methods and apparatus that enable access to and from a data storage device requiring significantly fewer actual address bits. In addition, some embodiment may significantly reduce the propagation delays inherent in current memory devices. In some embodiments, the devices do not need to store data and only the methods and systems for addressing uniquely addressable locations disclosed herein need be applied.
In one aspect of the present invention, a data storage device is disclosed. This aspect includes at least one addressing layer and at least one virtual column having at least one data storage element and a plurality of addressable switch elements. The at least one virtual column is coupled to the at least one addressing layer such that at least one of the plurality of addressable switch elements is in a conductive relationship with the at least one addressing layer.
In another aspect of the present invention, a device for storing data that includes at least one virtual column, at least one read layer coupled to a first portion of the virtual column and at least one addressing layer coupled to a second portion of the virtual column is disclosed.
In another aspect, a data storage device comprising a plurality of virtual columns is disclosed. In this aspect, each of the virtual columns includes an addressable switch element and a data storage element. This aspect also includes, surrounding the addressable switch element, a material adapted to transmit a signal to the addressable switch element.
In another aspect, a data storage device is disclosed. In this aspect the device includes a plurality of memory devices, each containing data storage elements, configured such that each data storage element contained in each memory device is accessible for read/write operations by presenting an address of the data storage element to a plurality of laminar layers contained in the device. In this aspect, each memory device includes a plurality of external access lines associated with a respective one of the plurality of laminar layers. This aspect also includes a plurality of external bus bars, that is associated with at least one of the plurality of external access lines.
In another aspect, a memory device that includes a first strip of non-conductive material and a first plurality of virtual columns disposed on the first strip is disclosed.
In another aspect, a memory device comprising a substrate and a plurality of virtual columns arranged into sections on the substrate is disclosed. In this aspect, each section including a plurality of address lines coupled to portions of the virtual columns. This aspect also includes a plurality of external access lines coupled to the address lines.
In another aspect of the present invention, a method of accessing data in a data storage device having a plurality of layers is disclosed. The method of this aspect includes steps of (a) determining an address of a data bit to be accessed, and (b) applying a voltage to the plurality of address layers, wherein the voltage applied to the plurality of address layers corresponds to a logic state of a particular bit expressed by a binary representation of the address.
In another aspect, a method of accessing data in a data storage device having a plurality of layers is disclosed. The method of this aspect includes steps of: (a) determining an address of a data bit to be accessed, and (b) applying a voltage to the plurality of address layers, where the voltage applied to each address layer corresponds to a logic state of a particular bit expressed by the binary representation of the address.